Kurage Notes

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Intro to RISC-V ​

Assembly Languages ​

Instruction Set Architecture (ISA)

  • A set of available operations implemented by a specific type of CPU
  • Describe almost any behaviour
  • ISA defines an assembly language

With assembly languages, almost everything is explicitly handled by the programmer.

RISC ​

Reduced Instruction Set Computer

  • Instruction set simple and small
  • Software do complicated operations

RISC-V ​

https://cs61c.org/su24/pdfs/resources/reference-card.pdfhttps://venus.cs61c.org/

  • RISC-V is little endian

Design Principle ​

  1. Simplicity favours regularity
  2. Smaller is faster
  3. Good design demands good compromises

RISC-V Registers ​

Overview ​

  • A RISC-V system is composed of two main parts:
    • The CPU, which is responsible for computing
    • Main memory, which is responsible for long-term data storage
  • The CPU is designed to be extremely fast, often completing multiple instructions every nanosecond
  • Going to main memory often takes hundreds or even thousands of nanoseconds.
  • The CPU can store a small amount of data, through components called registers.

Registers ​

  • A register is a CPU component designed to store a small amount of data.
  • Each register stores 32 bits of data (for a 32-bit system) or 64 bits of data (for a 64-bit system). In this class, we use 32-bit only.
  • RISC-V gives access to 32 registers
  • The size and number of registers is fixed (you can think of them as being implemented in hardware)

Registers in RISC-V ​

  • RISC-V gives access to 32 registers
  • Registers are numbered from 0 to 31
    • Referred to by number: x0 – x31
  • The register x0 is special and always stores 0 (trying to write data to that register results in the write being ignored). As such, we have 31 registers available for data storage
  • The other 31 registers are all identical in behavior; the only difference between different registers is the conventions we follow when using them.